The present disclosure relates to digital circuits, and in particular, to digital circuits with compressed carry.
Digital circuits process logical signals represented by zeros (0) and ones (1) (i.e., bits). A digital multiplier is an electronic circuit capable of receiving two digital input values and determining a product of the two input values. Performing multiplication digitally can raise a number of challenges. For example, digital multipliers may comprise large arrays of adders and other circuits that can introduce delays in the various signals generated during the multiplication process and reduce the speed of the multiplication process. As another example, large numbers of interconnect wires may be required to route intermediate signals between various circuit components, which increases the area of the circuit and may cause processing delays if the wires run long distances, for example. As yet another example, numeric values in a digital system are represented by digital bits. When numbers represented by digital values are combined, errors relating to quantization and the limited accuracy of digital systems may occur, which can result in a loss of numeric accuracy, for example. In applications that require large numbers of accurate multiplications or additions, or both, these and other constraints may reduce the performance of the system.
One particular application where digital multiplication and/or addition are used extensively is machine learning (aka artificial intelligence). Such applications may require particularly fast, efficient, and/or accurate multipliers and/or adders to carry out various system functions.
The present disclosure provides improved architectures for digital circuits that process numeric values.